The present invention relates to hybrid circuits and devices fabricated from superconductor materials combined with semiconductor devices that can be operated at low temperatures. More particularly the present invention relates to superconducting field effect transistor-like devices, sometimes called JOFETs for Josephson FETs or SFETs for superconducting FETs, and improvements to the utility of such devices when used in combination with low temperature CMOS devices in applications such as high speed, low power consumption memory and logic circuits. The present invention makes use of superconductive materials with low critical temperatures (T.sub.c .ltoreq.20 K.) as well as superconductive materials with high critical temperatures (T.sub.c &gt;20 K.).
2. Description of the Related Art
The discovery of superconductors whose critical temperatures are above liquid nitrogen temperature prompted increased interest in hybrid superconducting-semiconducting electronic circuit applications. The possibilities for using superconducting devices for interconnecting conventional semiconductor circuits and devices have been studied. See for example, "Superconductor-Semiconductor Hybrid Devices, Circuits and Systems," Kroger, et al., Proceedings of the IEEE, Vol. 77, No. 8, Aug. 1989; T. van Duzer, "Superconductor-Semiconductor Hybrid Devices, Circuits and Systems," Cryogenics, Vol. 28, pp. 527-531 (1988); H. Kroger, "Josephson Devices Coupled by Semiconductor Links," IEEE Trans. Electron Devices, Vol. ED-27, pp. 2016-2126 (1980).
Prior art investigation and fabrication of hybrid three-terminal devices has led to the general conclusion that such devices are interesting but essentially useless in an engineering sense. The motivation for developing such devices has been to improve upon the gain and isolation available from conventional Josephson tunnel junctions, as well as to provide an active device which can perform all the conventional circuit functions as transistor circuits.
Superconducting Field Effect Transistors have been fabricated. FIG. 1 illustrates a superconducting FET structure. The superconducting FET is similar to conventional semiconductor FET structure, except that the source and drain must be superconductors. Devices constructed to date have a channel length in the range of 0.1 to 1.0 .mu.m. The function of a superconducting FET is similar to that of a conventional semiconductor FET, but it makes use of a conduction mechanism characteristic of superconductivity known as the proximity effect. Compared to the tunnel junctions thin barrier (10-60 nm) the greater channel length of the superconducting FET implies that the transport mechanism cannot be the tunnel effect. Superconducting electrons can diffuse into a doped semiconductor and make it weakly superconductive. This is called the proximity effect. The doped semiconductor need not be degeneratively doped since an inversion layer can also support a supercurrent and the material in which the inversion layer is formed need not be degeneratively doped.
Superconducting FETs function in analogy to semiconducting FETs in that the gate voltage controls the current flowing from the source to the drain. In superconducting FETs, the magnitude of a zero-voltage current can be controlled by the gate electrode. The drain of the device is either in a voltage state (on the order of tens of millivolts) or exactly at zero voltage. The SFET is unique in that it has a nonzero transconductance when the drain-to-source voltage is zero. No semiconductor FET has this property. One hope for such devices has been that they would provide fast switching with very low power dissipation. No matter which configuration is utilized, a minimum gate voltage is required to turn on or turn off a zero-voltage drain current. The only superconducting FETs studied to date were fabricated from low-temperature superconductors and are considered to be of little practical importance because they have zero power gain and do not produce an output voltage signal large enough to enable an SFET string of logic gates to be operated without additional logic level voltage restoration.
Many weak couplings of two superconductors show the Josephson effect. Such weak couplings include tunneling barriers, geometric constrictions in the superconductors themselves, and films of normal metals thinner than several hundreds of nanometers. These structures are called weak links.
For a normal metal weak link the critical current, I.sub.c, is a function of the normal carrier density in the link. I.sub.c is proportional to exp (-L/.xi.n) where L is the length of the link and n is the coherence length in the normal metal. .xi.n is given by: EQU .xi.n= .sup.3 .mu./6.pi.m.sup.* ekT).sup.1/2 (3.pi..sup.2 n).sup.1/3
Where is the reduced Planck constant, m is the carrier mobility, T is the absolute temperature, m.sup.* is the carrier effective mass, k is Boltzmann's constant, and n is the carrier density in the normal metal. Values of the coherence length in degeneratively doped semiconductors are typically a few hundred nanometers at 4.2 K. and lower temperatures.
A number of proposals have been made to develop superconducting three terminal devices analogous to semiconductor FETs. See for example, A. W. Kleinsasser and T. N. Jackson, "Superconductivity and field effect transistors," in Proc. 18th Int. Conf. on Low Temperature Physics (Kyoto); Jpn.J.Appl.Phys., Vol. 26, pp. 1545-1546, 1987; M. F. Millea, A. H. Silver, and L. D. Flesner, "Superconductivity contact to p-InAs," IEEE Trans. Magn., Vol. MAG-15, pp. 435-438, 1979; A. H. Silver, A. B. Chase, M. McCall, and M. F. Millea, "Superconductor-semiconductor device research," in Future Trends in Superconductive Electronics, B. S. Dever, C. M. Falco, J. H. Harris, and S. A. Wolf, Eds. New York, N.Y.: Am. Inst. of Physics, 1978, pp. 368-379; T. D. Clark, R. J. Prance, and A. D. C. Grassie, "Feasibility of hybrid Josephson field effect transistors," J.Appl.Phys., Vol. 51, pp. 2736-2745, 1980; A. W. Kleinsasser et al., "Semiconductor heterostructure weak links for superconducting FET applications," IEEE Trans. Magn., Vol. MAG-23, pp. 703-706, 1987; Z. Ivanov and T. Claeson, "A three terminal Josephson junction with a semiconducting two-dimensional electron gas layer," IEEE Trans. Magn., Vol. MAG-23, pp. 711-713, 1987; T. Nichino and U. Kawabe, "Realization of semiconductor-coupled superconducting transistor," in Proc. 2nd Int. Symp. Foundations of Quantum Mechanics (Tokyo), pp. 231-240, 1986; T. Nichino, M. Miyake, Y. Harada, and U. Kawabe, "Three-terminal superconducting devices using a Si single-crystal film," IEEE Electron Device Lett., Vol. EDL-6, pp. 297-299, 1985; Z. Ivanov, T. Claeson, and T. Anderson, "Three terminal Josephson junction with a semiconductor accumulation layer," in Proc. 18th Int. Conf. on Low Temperature Physics (Kyoto); Jpn. J. Appl. Phys., Vo.. 26, pp. 1617-1618, 1987; H. Takayangi and T. Kawakami, "Superconducting proximity effect in the native inversion layer on InAs," Phys. Rev. Lett., Vol. 55, pp. 2449-2452, June 3, 1985. All these proposed devices function by changing the carrier density in the region under the gate, and thus the critical current in accordance with the equation given above for .xi.n. Actual reductions to practice have been made for structures using silicon, InAs or GaAs as the semiconductor portion of the device.
FIG. 2 represents the source-drain current-voltage (I-V) characteristics of a typical three-terminal superconducting FET. The inverse slope of the characteristics in the voltage state is the normal resistance R.sub.N of the device. The critical current I.sub.C is the maximum zero-voltage (Josephson) current which can flow between source and drain of the device. If the bias current I.sub.b is less than I.sub.C, then the voltage between source and drain is exactly zero. In a three-terminal superconducting FET, I.sub.C is controlled by the voltage applied to the gate electrode.
FIG. 3 is a schematic diagram of a typical superconductive FET inverter assuming the device works in the enhancement mode. As shown, the truth table for the device gate is:
______________________________________ Vin Vout ______________________________________ O V.sub.dd (&gt;V.sub.crit) V.sub.dd (&gt;V.sub.crit) I.sub.d R.sub.n ______________________________________
This circuit can be used in a string of logic gates (shown in phantom) only if I.sub.d R.sub.N &gt;V.sub.crit, that is, if the product of the bias current and normal resistance of the weak link is greater than V.sub.crit, the voltage required to induce a zero-voltage output in the following device. However, for all demonstrated devices in the prior art, I.sub.b R.sub.N is significantly less than V.sub.crit. This is why superconducting FETs of the prior art have been considered impractical.
In the circuit of FIG. 3, the bias current I.sub.b must be less than the maximum possible critical current I.sub.C in order to ensure that the device operates in the zero-voltage state. Therefore, a more general requirement for superconducting FETs is that I.sub.C R.sub.N &gt;V.sub.crit. For all known SFETs it has been observed that the I.sub.C R.sub.N product is significantly less than the required critical gate voltage of a subsequent device. Some studies have suggested that possible improvements to this situation might be obtained by fabricating superconductive FETs with high temperature superconductive elements. See for example, A. W. Kleinsasser and T. N. Jackson, "Prospects for proximity effect superconducting FETs," IEEE Trans. Magn., vol. MAG-25, pp. 1274-1277, 1989. These researchers conclude that a higher I.sub.C R.sub.N product might make possible the fabrication of devices with gain, but that such conclusion rests upon optimistic assumptions regarding material parameters and theory. Furthermore, despite extensive research, a number of theoretical questions persist concerning the operation of high temperature superconductive FETs which may effect whether practical FETs can be fabricated even with assumed improvements achieved with high temperature superconductor materials.